1 fn6792.1 ISL8840AMZ, isl884 1amz, isl8842amz, isl8843amz, isl884 4amz, isl8845amz high performance industry standard single-ended current mode pwm controller the isl884xambepz is a hi gh performance drop-in replacement for the popular 28c4x and 18c4x pwm controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. its fast si gnal propagation and output switching characteristics make this an ideal product for existing and new designs. features include 30v operation, low operating current, 90a start-up current, adjustable operating frequency to 2mhz, and high peak current drive capability with 20ns rise and fall times. pinout isl884xambepz (8 ld soic) top view features ? full mil-temp electrical perf ormance from -55c to +125c ? controlled baseline with one wafer fabrication site and one assembly/test site ? full homogenous lot processing in wafer fab ? no combination of wafer fabrication lots in assembly ? full traceability through assembly and test by date/trace code assignment ? enhanced process change notification ? enhanced obsolescence management ? eliminates need for up-screening a cots component ? 1a mosfet gate driver ? 90a start-up current, 125a maximum ? 35ns propagation delay current sense to output ? fast transient response with peak current mode control ? 30v operation ? adjustable switching frequency to 2mhz ? 20ns rise and fall times with 1nf output load ? trimmed timing capacitor di scharge current for accurate deadtime/maximum duty cycle control ? 1.5mhz bandwidth error amplifier ? tight tolerance voltage reference over line, load and temperature ? 3% current limit threshold ? pb-free (rohs compliant) applications ? isolated flyback and forward regulators ? boost regulators part number rising uvlo (v) max. duty cycle (%) isl8840ambepz 7.0 100 isl8841ambepz 7.0 50 isl8842ambepz 14.4 100 isl8843ambepz 8.4 100 isl8844ambepz 14.4 50 isl8845ambepz 8.4 50 comp fb rtct vref vdd out gnd 1 2 3 4 8 cs 7 6 5 data sheet december 1, 2011 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2008, 2011. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6792.1 december 1, 2011 ordering information part number (notes 1, 2) part marking temp range (c) package (pb-free) pkg. dwg. # isl8840ambepz 8840a mbepz -55 to +125 8 ld soic m8.15 isl8841ambepz 8841a mbepz -55 to +125 8 ld soic m8.15 isl8842ambepz 8842a mbepz -55 to +125 8 ld soic m8.15 isl8843ambepz 8843a mbepz -55 to +125 8 ld soic m8.15 isl8844ambepz 8844a mbepz -55 to +125 8 ld soic m8.15 isl8845ambepz 8845a mbepz -55 to +125 8 ld soic m8.15 notes: 1. add ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
3 fn6792.1 december 1, 2011 functional block diagram t q q on 150k 100k v dd cs out fb rtct gnd vref pwm comparator reset dominant 2.5v enable 8.4ma 2.9v 1.0v oscillator comparator <10ns + - start/stop uv comparator v ref 5.00v + - + - 100mv error amplifier + - vref + - on + - s r q q comp vref uv comparator 4.65v 4.80v + - a = 0.5 + - clock 1.1v clamp 2r r vf total = 1.15v a vref fault ok v dd 36k isl8841ambepz/ only isl8844ambepz/ isl8845ambepz ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
4 fn6792.1 december 1, 2011 absolute maximum rati ngs thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to +30v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to v dd + 0.3v signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a thermal resistance (note 4) ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions supply voltage range (note 3) . . . . . . . . . . . . . . . . . . . . . 9v to 30v temperature range . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. all voltages are with respect to gnd. 4. ja is measured with the component mounted on a high effective therma l conductivity test board in fr ee air. see technical brief tb 379 for details. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 3. v dd = 15v, r t = 10k , c t = 3.3nf, t a = -55 to +125c, typical values are at t a = +25c. parameters with min and/or max limits are 100% tested at +25c, unless ot herwise specified. temperat ure limits established by characterization and are not production tested parameter test conditions min typ max units undervoltage lockout start threshold (isl8840ambepz, isl8841ambepz) 6.5 7.0 7.5 v start threshold (isl8843ambepz, isl8845ambepz) 8.0 8.4 9.0 v start threshold (isl8842ambepz, isl8844ambepz) (note 7) 13.3 14.3 15.3 v stop threshold (isl8840ambepz, isl8841ambepz) 6.1 6.6 6.9 v stop threshold (isl8843ambepz, isl8845ambepz) 7.3 7.6 8.0 v stop threshold (isl8842ambepz, isl8844ambepz) 8.0 8.8 9.6 v hysteresis (isl8840ambepz, isl8841ambepz) - 0.4 - v hysteresis (isl8843ambepz, isl8845ambepz) - 0.8 - v hysteresis (isl8842ambepz, isl8844ambepz) - 5.4 - v start-up current, i dd v dd < start threshold - 90 125 a operating current, i dd (note 5) - 2.9 4.0 ma operating supply current, i d includes 1nf gate loading - 4.75 5.5 ma reference voltage overall accuracy over line (v dd = 12v to 30v), load, temperature 4.900 5.000 5.050 v long term stability t a = +125c, 1000 hours (note 6) - 5 - mv current limit, sourcing -20 - - ma current limit, sinking 5- -ma current sense input bias current v cs = 1v -1.0 - 1.0 a cs offset voltage v cs = 0v (note 6) 95 100 105 mv comp to pwm comparator offset voltage v cs = 0v (note 6) 0.80 1.15 1.30 v input signal, maximum 0.97 1.00 1.03 v ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
5 fn6792.1 december 1, 2011 gain, a cs = v comp / v cs 0 < v cs < 910mv, v fb = 0v 2.5 3.0 3.5 v/v cs to out delay -3560ns error amplifier open loop voltage gain (note 6) 60 90 - db unity gain bandwidth (note 6) 1.0 1.5 - mhz reference voltage v fb = v comp 2.460 2.500 2.535 v fb input bias current v fb = 0v -1.0 -0.2 1.0 a comp sink current v comp = 1.5v, v fb = 2.7v 1.0 - - ma comp source current v comp = 1.5v, v fb = 2.3v -0.4 - - ma comp voh v fb = 2.3v 4.80 - vref v comp vol v fb = 2.7v 0.4 - 1.0 v psrr frequency = 120hz, v dd = 12v to 30v (note 6) 60 80 - db oscillator frequency accuracy initial, t a = +25c 48 51 53 khz frequency variation with v dd t a = +25c, (f 30v - f 10v )/f 30v -0.21.0% temperature stability (note 6) - - 5 % amplitude, peak-to-peak static test - 1.75 - v rtct discharge voltage (valley voltage) static test - 1.0 - v discharge current rtct = 2.0v 6.2 8.0 8.5 ma output gate voh v dd - out, i out = -200ma - 1.0 2.0 v gate vol out - gnd, i out = 200ma - 1.0 2.0 v peak output current c out = 1nf (note 6) - 1.0 - a rise time c out = 1nf (note 6) - 20 40 ns fall time c out = 1nf (note 6) - 20 40 ns gate vol uvlo clamp voltage v dd = 5v, i load = 1ma - - 1.2 v pwm maximum duty cycle (isl8840ambepz, isl8842ambepz, isl8843ambepz) comp = vref 94.0 96.0 - % maximum duty cycle (isl8841ambepz, isl8844ambepz, isl8845ambepz) comp = vref 47.0 48.0 - % minimum duty cycle comp = gnd - - 0 % notes: 5. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 6. limits established by characteri zation and are not production tested. 7. adjust v dd above the start threshold and then lower to 15v. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 3. v dd = 15v, r t = 10k , c t = 3.3nf, t a = -55 to +125c, typical values are at t a = +25c. parameters with min and/or max limits are 100% tested at +25c, unless other wise specified. temperature limits established by characterization and are not production tested (continued) parameter test conditions min typ max units ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
6 fn6792.1 december 1, 2011 pin descriptions rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, r t , between v ref and this pin and a timing capacitor, c t , from this pin to gnd. the oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f, and the maximum duty cycle, d max , can be approximated from the following equations: the formulae have increased error at higher frequencies due to propagation delays. figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is connected between the comp and fb pins. fb - the output voltage feedback is connected to the inverting input of the error amplifier through this pin. the non-inverting input of the error amplifier is internally tied to a reference voltage. cs - this is the current sense input to the pwm comparator. the range of the input signal is nominally 0v to 1.0v and has an internal offset of 100mv. gnd - gnd is the power and small signal reference ground for all functions. out - this is the drive output to the power switching device. it is a high current output capable of driving the gate of a power mosfet with peak currents of 1.0a. this gate output is actively held low when v dd is below the uvlo threshold. v dd - v dd is the power connection for the device. the total supply current will depend on the load applied to out. total i dd current is the sum of th e operating current and the average output current. knowing the operating frequency, f, typical performance curves figure 1. frequency vs temperature figure 2. reference voltage vs temperature figure 3. ea reference vs temperature figure 4. resistance for ct capacitor values given -60 -40 -20 0 20 40 60 80 100 120 140 0.98 0.99 1.00 1.01 temperature (c) normalized frequency -60 -40 -20 0 20 40 60 80 100 0.995 0.996 0.997 0.998 0.999 1.000 1.001 temperature (c) normalized v ref 140 120 -60 -40 -20 0 20 40 60 80 100 120 140 0.996 0.997 0.998 1.000 1.001 temperature (c) normalized ea reference 110100 1 10 100 10 3 r t (k ) frequency (hz) 100pf 220pf 330pf 470pf 1.0nf 2.2nf 3.3nf 4.7nf 6.8nf t c 0.533 r t c t ?? (eq. 1) t d r t ? c t in 0.008 r t 3.83 ? ? 0.008 r t 1.71 ? ? ------------------------------------------ - ? ? ? ? ? ? ?? (eq. 2) f 1t c t d + () ? = (eq. 3) dt c f ? = (eq. 4) ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
7 fn6792.1 december 1, 2011 and the mosfet gate charge, qg, the average output current can be calculated from equation 5: to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the v dd and gnd pins as possible. vref - the 5.00v reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. bypass to gnd with a 0.1f to 3.3f capaci tor to filter this output as needed. functional description features the isl884xambepz current mode pwm makes an ideal choice for low-cost flyback and forward topology applications. with its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. oscillator the isl884xambepz has a sa wtooth oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor from v ref and a capacitor to gnd on the rtct pin. (please refer to figure 4 for the resistor and capacitance required for a given frequency.) soft-start operation soft-start must be implemented externally. one method, illustrated in figure 5, clamps the voltage on comp. the comp pin is clamped to the voltage on capacitor c 1 plus a base-emitter junction by transistor q 1 . c 1 is charged from vref through resistor r 1 and the base current of q1. at power-up c 1 is fully discharged, comp is at ~0.7v, and the duty cycle is zero. as c 1 charges, the voltage on comp increases, and the duty cycle in creases in proportion to the voltage on c 1 . when comp reaches the steady state operating point, the control loop takes over and soft-start is complete. c 1 continues to charge up to v ref and no longer affects comp. during power-down, diode d 1 quickly discharges c 1 so that the soft-start circuit is properly initialized prior to the next power-on sequence. gate drive the isl884xambepz is capable of sourcing and sinking 1a peak current. to limit the peak current through the ic, an optional external resistor may be placed between the totem-pole output of the ic (out pin) and the gate of the mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. slope compensation for applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ra mp from the voltage feedback error signal. adding the exte rnal ramp to the current feedback signal is the more popular method. from the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, fm, without slope compensati on, is in equation 6. where s n is the slope of the sawtooth signal and t sw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes equation 7: where s e is slope of the external ramp and the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-po le located at the switching frequency. the double-pole will be critically damped if the q-factor is set to 1, over-damped for q < 1, and under-damped for q > 1. an under-damped condition may result in current loop instability. i out qg f = (eq. 5) figure 5. soft-start vref comp gnd isl884xambepz c1 q1 d1 r1 fm 1 s n t sw ----------------- - = (eq. 6) fm 1 s n s e + () t sw ------------------------------------ 1 m c snt sw -------------------------- - == (eq. 7) m c 1 s e s n ------ - + = (eq. 8) q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 9) ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
8 fn6792.1 december 1, 2011 where d is the percent of on- time during a switching cycle. setting q = 1 and solving for s e yields equation 10: since s n and s e are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal ( i) during the on-time and v e is the voltage that must be added by the external ramp. for a flyback converter, v n can be solved for in terms of input voltage, current transducer components, and primary inductance, yielding where r cs is the current sense resistor, f sw is the switching frequency, l p is the primary inductance, v in is the minimum input voltage, and d is the maximum duty cycle. the current sense signal at the end of the on-time for ccm operation is: where v cs is the voltage across the current sense resistor, l s is the secondary winding inductance, and i o is the output current at current limit. equation 13 assumes the voltage drop across the output re ctifier is negligible. since the peak current limit threshold is 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold. substituting equations 12 and 13 into equation 14 and solving for r cs yields equation 15: adding slope compensation is accomplished in the isl884xambepz using an external buffer transistor and the r t c t signal. a typical application sums the buffered r t c t signal with the current sense feedback and applies the result to the cs pin, as shown in figure 6. assuming the designer has selected values for the rc filter (r 6 and c 4 ) placed on the cs pin, the value of r 9 required to add the appropriate external ramp can be found by superposition. the factor of 2.05 in equati on 16 arises from the peak amplitude of the sawtooth waveform on r t c t minus a base-emitter junction drop. that voltage multiplied by the maximum duty cycle is the volt age source fo r the slope compensation. rearranging to solve for r 9 yields: the value of r cs determined in equation 15 must be rescaled so that the current s ense signal presented at the cs pin is that predicted by equation 13. the divider created by r 6 and r 9 makes this necessary. example: v in = 12v v o = 48v l s = 800h ns/np = 10 l p = 8.0h i o = 200ma switching frequency, f sw = 200khz duty cycle, d = 28.6% s e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 10) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 11) v e dt ? sw v in r cs ?? l p -------------------------------------------------- 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = v (eq. 12) v cs n s r cs ? n p ------------------------ i o 1d ? () v o f ?? sw 2l s ---------------------------------------------- + ?? ?? ?? = v (eq. 13) v e v cs + 1 = (eq. 14) r cs 1 df sw v in ?? l p ------------------------------- 1 -- - 0.5 + 1d ? ----------------- - 1 ? ?? ?? ?? ?? ? n s n p ------ - i o 1d ? () v o f sw ?? 2l s -------------------------------------------- + ?? ?? ?? ? + ------------------------------------------------------------------------------------------------------------------------------- --------------------- - = (eq. 15) cs rtct r6 c4 r9 isl8843 vref figure 6. slope compensation v e 2.05d r 6 ? r 6 r 9 + --------------------------- - = v (eq. 16) r 9 2.05d v e ? () r 6 ? v e --------------------------------------------- - = (eq. 17) r cs r 6 r 9 + r 9 -------------------- - r cs ? = (eq. 18) ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
9 fn6792.1 december 1, 2011 r 6 = 499 solve for the current sense resistor, r cs , using equation 15. r cs = 295m determine the amount of voltage, v e , that must be added to the current feedback signal using equation 12. v e = 92.4mv using equation 17, solve for the summing resistor, r 9 , from ct to cs. r 9 = 2.67k determine the new value of r cs (r? cs ) using equation 18. r? cs = 350m additional slope compensation may be considered for design margin. the previous discussion determines the minimum external ramp that is required. the buffer transistor used to create the external ramp from r t c t should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base curr ent is required reduces the charging current into r t c t and will reduce the oscillator frequency. fault conditions a fault condition occurs if v ref falls below 4.65v. when a fault is detected, out is disabled. when v ref exceeds 4.80v, the fault condition clears, and out is enabled. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. v dd should be bypassed directly to gnd with good high frequency capacitors. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee tr ansactions on power electronics, vol. 6, no. 2, april 1991. ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6792.1 december 1, 2011 ISL8840AMZ, isl8841amz, isl8842amz, isl8843amz, isl8844amz, isl8845amz small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
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